1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to those having a redundant, repairing spare memory cell.
2. Description of the Background Art
Recently there has been provided a semiconductor memory device having a memory cell array configuration to provide a wide data I/O width to accommodate some applications, such as an image processing requiring a wide memory band width.
Representatively, there has been developed a merged DRAM/logic with a logic portion and a dynamic random access memory (DRAM) both mounted on a single chip. In this memory, an I/O pin and an external bus that conventionally exist between a processor portion and a DRAM core can be eliminated to allow data to be transferred with high degree of freedom and a large number of global data input/output lines allowing data to be simultaneously input/output to/from the DRAM core can be provided to achieve a wide data I/O width.
In a merged memory/logic a logic portion and a DRAM core have much more global data input/output lines arranged therebetween than in a general-purpose memory, reaching more than 200 or more than 500 in number. In a merged memory/logic, a memory core incorporated therein is tested using data transmitted on such global data input/output lines, although a memory tester or a similar external test apparatus can only make a decision on limited data at a time. Furthermore, to efficiently test an operation a plurality of memory cores need to be tested simultaneously in parallel.
As such, the merged memory/logic typically has mounted therein a circuit operating in the operation test to select some of a large number of global data input/output lines arranged in parallel and output to an external test apparatus the data transmitted on the selected global data input/output line.
Furthermore, a large-scale memory core mounted in a merged memory/logic has a spare memory cell provided for each predetermined segment of regular memory cell arrays to repair a defective regular memory cell to improve the yield of the device. In general, a spare memory cell operation test is conducted separately from a regular memory cell operation test. Both of a result of testing a spare memory cell and that of testing a regular memory cell are used for determining a substitution pattern for redundancy to repair a defective memory cell.
A large-scale memory core has a large area occupied by spare memory cells. As such, it is important that not only a regular memory cell operation test but a spare memory cell operation test be conducted efficiently.
FIG. 12 is a block diagram for illustrating conventionally selecting output data in a testing operation. FIG. 12 exemplarily illustrates that in the testing operation, hereinafter also referred to as the xe2x80x9ctest modexe2x80x9d, eight testing output data TDout are output for a single read operation.
With reference to FIG. 12, a memory cell array subject to an operation test is configured of a plurality of memory mats each corresponding to a predetermined segment of a regular memory cell array. FIG. 12 exemplarily shows a memory cell array formed of eight memory mats MT0 to MT7.
256 regular global data input/output lines GIO(0) to GIO(255) are arranged to transmit data input/output to/from a regular memory cell of the memory cell array. Each memory mat is provided with a spare memory cell arranged therefor, and to transmit data input/output to/from a spare memory cell there are provided spare global data input/output lines SGIO(0) to SGIO(7) for memory mats MT0 to MT7, respectively.
Regular global data input/output lines GIO(0) to GIO(255) are divided into a plurality of groups of eight lines, which number corresponds to the number of the data output in the testing operation, and the eight regular global data input/output lines of each group are gathered at a respective one of internal node groups N0-N31. For example, at internal node group N0 are gathered regular global data input/output lines GIO(0) to GIO(7).
To accommodate a spare memory cell operation test, spare select circuits 510-0 to 510-7 are provided for memory mats MT0 to MT7, respectively. Each spare select circuit receives as an input thereof one of the regular global data input/output lines for a single memory mat and a spare global data input/output line and in response to a test mode signal STMOD outputs data transmitted on either one of the regular and spare global data input/output lines. Test mode signal STMOD is activated when a spare memory cell has its operation to be tested in the test mode, and it is otherwise inactivated.
For example, spare select circuit 510-0 receives regular global data input/output line GIO(0) and spare global data input/output line SGIO(0) and outputs data transmitted on spare global data input/output line SGIO(0) for active mode signal STMOD and data transmitted on regular global data input/output line GIO(0) for inactive mode signal STMOD.
Spare select circuits 510-0 to 510-7 operate in response to the common mode control signal STMOD. As such, if a spare memory cell has its operation to be tested, in each memory mat for any one of the plurality of node groups there can be read the data transmitted on a spare global data input/output line.
A selector circuit 520 selects any one of internal node groups N0 to N31 in response to select signals SEL0 to SEL4 and outputs eight data corresponding to the selected internal node group.
If a spare memory cell has its operation to be tested, select signals SEL0 to SEL4 can be changed to select internal node groups N0, N4, . . . , N28, corresponding to spare select circuits 510-0 to 510-7, successively one at a time, to output data output from each memory mat and transmitted on a spare global data input/output line to an external testing apparatus.
If in such a configuration as above a spare memory cell has its operation tested, however, of eight testing output data from selector circuit 520 only one data corresponds to a spare memory cell and the other seven data are irrelevant to the spare memory cell operation test. This means that testing data are uselessly output. In the FIG. 12 configuration, outputting the data transmitted on all of spare global data input/output lines SGIO(0) to SGIO(7) requires performing a read operation eight times. As such, the spare memory cell operation test is time-consuming. Furthermore, of a plurality of data output from selector circuit 520 the data output corresponding to a spare memory cell needs to be recognized by an external testing apparatus. This complicates a program in conducting the operation test.
In testing a spare memory cell, generating the test mode has a disadvantage, as will be described below.
FIG. 13 is a block diagram for illustrating conventionally decoding a command.
With reference to FIG. 13, any one of 23=eight commands is produced according to a combination in level of three command control signals of a row address strobe signal /RAS, a column address strobe signal /CAS and a write enable signal /WE.
The produced command is any one of no-operation command (NOP), an activation command (ACT), a read command (READ), a write command (WRT), a precharge command (PRE), a mode set command (MST), an auto-refresh command (AREF) and a self-refresh command (SREF).
The group of these commands are produced by a logic gate group LG50. If mode set command MST is produced, a mode set sequence is also started. In the mode set sequence, one of a plurality of modes set in a mode table 530 is selected according to a combination in level of address signals A0 to A10 input to an address terminal.
When read command READ is produced, mode table 530 is referred to to selectively perform either one of an operation reading a regular memory cell and that reading a spare memory cell. Similarly, when write command WRT is produced, the mode table is referred to to perform an operation writing data to either one of a regular memory cell and a spare memory cell.
FIG. 14 is timing plots for illustrating a spare memory cell operation test based on conventionally decoding a command.
With reference to FIG. 14, at each of times T0 to T5, each corresponding to a timing at which a clock signal is activated, command control signals are taken in and according to a combination in level of the command control signals a command is produced.
At timing T0 and timing T1 of clock activation a read command READ1 and a read command READ2 are respectively produced for a regular memory cell, and, with a CAS latency of one clock cycle, at time T1 and time T2 output data D1 and D2 are output corresponding to read commands READ1 and READ2, respectively.
Testing an operation of a spare memory cell array requires starting the mode set sequence to change a selection of mode table 530. At time T2, a command control signal and an address signal have their respective signal levels set as appropriate to produce mode set command MST and mode table 530 has a mode selection switched to a spare mode provided to access the spare memory cell array.
Thereafter when at time T3 and time T4 read commands READ3 and READ4 are produced a spare memory cell can be read. At time T4 and time T5, from the spare memory cell there can be output testing output data D3 and D4.
Thus, switching from a normal read command for a regular memory cell to a read command for a spare memory cell requires performing a mode set sequence independently requiring one clock cycle. As such, a regular memory cell and a spare memory cell cannot be accessed in successive clock cycles. As such, there cannot be conducted a test examining how a normal word line for a normal memory cell and a spare word line adjacent thereto interfere with each other, a test continuously accessing physically contiguous memory cell rows at predetermined intervals, and the like.
The present invention contemplates a configuration of a semiconductor memory device capable of efficiently testing an operation of a spare memory cell provided to repair a defective portion of a regular memory cell.
Briefly speaking, the present intention provides a semiconductor memory device outputting N data for one read operation in a test mode, N representing a natural number, including a memory cell array, a plurality of regular data input/output lines, a plurality of spare data input/output lines, a first testing output select circuit, a second testing output select circuit and a third testing output select circuit.
The memory cell array is divided into a plurality of memory mats, each including a plurality of regular memory cells arranged in rows and columns and a plurality of spare memory cells provided to substitute and thus repair a defect of the plurality of regular memory cells. The plurality of regular data input/output lines transmit data input to and output from the plurality of regular memory cells. The plurality of spare data input/output lines transmit data input to and output from the plurality of spare memory cells. The first testing output select circuit in the test mode operates to output N data transmitted on N regular data input/output lines of the plurality of regular data input/output lines. The second testing output select circuit in the test mode operates to output N data transmitted on N spare data input/output lines of the plurality of spare data input/output lines. The third testing output select circuit operates to selectively output either one of an output of the first testing output select circuit and an output of the second testing output select circuit depending on whether the plurality of regular memory cells or the plurality of spare memory cells are to be tested in the test mode.
The present invention in another aspect provides a semiconductor memory device including a memory cell array, a first input node, a second input node and a command decode circuit.
The memory cell array has a plurality of regular memory cells and a plurality of spare memory cells arranged in rows and columns.
The first input node receives a plurality of control signals. The second input node receives in a test mode a voltage level indicating whether the plurality of regular memory cells or the plurality of spare memory cells are to be tested.
The command decode circuit is taking therein an input received by the first input node and an input received by the second input node, and responds to a combination in level of the plurality of control signals and a level in voltage of the second input node to produce an operation command for the memory cell array.
The present invention in still another aspect provides a semiconductor memory device including a memory cell array, a regular word line, a spare word line, a refresh address generation circuit and a word line drive circuit.
The memory cell array has a plurality of regular memory cells and a plurality of spare memory cells arranged in rows and columns. L regular word lines are arranged corresponding to rows of the plurality of regular memory cells, respectively, L being a natural number represented by 2Mxe2x88x921 less than Lxe2x89xa62M, M being a natural number. N spare word lines are arranged corresponding to rows of the plurality of memory cells, respectively, L being a natural number less than 2M. The refresh address generation circuit generates a refresh address signal of (M+1) bits corresponding to a count value counted up in a predetermined period. The word line drive circuit selectively activates at least one of the L regular word lines and N spare word lines. The word line drive circuit operates in response to the refresh address signal of (M+1) bits when a refresh operation is instructed in a test mode.
As such a main advantage of the present invention is that in the test mode only read data transmitted on a spare data input/output line can be selectively output and a spare memory cell can thus be tested in a reduced period of time.
Furthermore, a clock cycle for switching modes is not required in switching a subject of an operation test between the regular memory cell array and the spare memory cell array. As such, in the test mode the regular memory cell array and the spare memory cell array can be successively accessed.
Furthermore, a refresh operation can be performed according to a refresh address larger by one bit than the number of bits corresponding to the number of regular word lines. As such, a refresh operation test for a regular word line and that for a spare word line can be collectively performed. Thus a spare memory cell can be tested efficiently.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.